Evaluation of Threshold Frequencies for Logic Single-Event Upsets at Bulk FinFET Technology Nodes

With modern integrated circuits (ICs) operating at the GHz range of operation, the single-event (SE) cross-section of an average logic circuit feeding data into a conventional latch has become comparable to the latch SE cross-section. Logic SE cross-sections at advanced FinFET technology nodes are analyzed to identify the "Threshold Frequencies" at which the logic SE cross-section for a typical logic circuit exceeds that of the latch following it. The Threshold Frequency as a function of particle LET, supply voltage, and latch design are analyzed for the 16-nm, 7-nm, and 5-nm bulk FinFET technology nodes. Results show that the Threshold Frequency is of the order of 100's of MHz at these nodes for all test conditions used in this study. Understanding the Threshold Frequency concept and trends will allow designers to harden circuits efficiently to meet design specifications with minimum performance penalty.