ABSTRACT Although parallel prefix adders (PPAs) optimize data path through prefix operators, Ling adders show exceptional computing performance. Compared to traditional adders, however, Ling adders require additional components for generating Ling carries, so they are more complex. This paper proposes an architecture for approximate Ling adders based on parallel prefix topologies, referred to as approximate parallel prefix Ling adders (AxPPLAs). It is realized by using approximate prefix operators (AxPOs) to simplify the exact function of Ling carries for some less significant bits. The more significant bits are accurately computed. Various parallel prefix topologies and approximate processing bits are implemented to balance hardware costs and computing accuracy. The proposed AxPPLAs are compared with state‐of‐the‐art designs in terms of hardware cost, accuracy, and other figures of merit. Experimental results show that the proposed 16‐bit AxPPLAs improve hardware efficiency by significantly reducing delay and energy by up to 38.51% and 19.46%, on average, respectively, while maintaining competitive accuracy.
Zhang et al. (Fri,) studied this question.