Clock Tree Synthesis is a critical stage in VLSI design, ensuring reliable and efficient clock signal distribution. An optimized clock tree minimizes skew and insertion delay, crucial for timing closure in high-frequency designs. Smaller technology nodes increase design complexity and impose stricter PPA constraints. This research emphasizes the importance of Clock Tree Synthesis in advanced technology nodes and highlights the adverse effects of suboptimal clock tree designs. Key design metrics such as silicon area, timing margins, and dynamic power are directly influenced by CTS. We propose systematic timing path balancing and architectural enhancements aimed at maximizing performance while minimizing resource overhead, thereby improving overall design robustness.
Praveenkumar et al. (Thu,) studied this question.