Raised or Recessed? Finding the Optimal Gate Architecture for Improving the Static Performance of Graphene Transistors

Key Points

• The research aims to determine the optimal gate architecture that enhances the static performance of graphene transistors.
• Comparative analysis of different gate architectures
• Evaluation of static performance metrics
• Utilization of modeling techniques to simulate transistor behavior
• Certain gate architectures significantly improve carrier mobility
• Optimized designs demonstrate enhanced static performance compared to traditional architectures