Logic locking is a widely adopted hardware obfuscation technique which can be further sub-categorised into static and dynamic approaches based on the nature of the employed key. Besides being susceptible to SAT and fault injection attacks, static logic locking is vulnerable to widespread compromise from a single key exposure or device breach. On the other hand, dynamic logic locking introduces complexities in resource utilisation, key management, design, and adaptability. In this work, we provide a comprehensive and up-to-date overview of existing IP Obfuscation techniques, highlighting their strengths, and potential vulnerabilities. We also propose, a hybrid logic locking technique that capitalises on the positive attributes of both static and dynamic logic locking methodologies while minimising their inherent limitations. An initial proof-of-concept implementation/simulation has been performed on the Xilinx SP605 FPGA development board. The suggested transient key logic locking scheme is applicable to all type of IPs.
Malik et al. (Thu,) studied this question.