The rapid proliferation of small satellite missions demands flight software that combines reliability, reusability, and rapid development cycles. NASA’s Core Flight System (cFS), with its layered architecture and component-based design, offers a promising solution. However, its resource-intensive design poses significant challenges for deployment on microcontroller (MCU) platforms commonly used in nanosatellites. This paper presents a comprehensive approach to porting cFS to the TMS570 safety microcontroller running FreeRTOS. We address critical challenges including Operating System Abstraction Layer (OSAL) adaptation for lightweight real-time operating systems and file system virtualization using RAM disk. As a core architectural contribution, we propose a hierarchical memory architecture that partitions high-speed internal RAM from external SDRAM, enabling all five cFE core services to operate within 256 KB on-chip RAM by offloading latency-tolerant data structures to SDRAM and releasing 37.5% of internal memory for mission applications. Performance evaluation yields two key quantitative findings: (1) Software Bus latency on SDRAM scales non-linearly from 1.85× to 7.67× relative to internal RAM as message size increases from 64 B to 4 KB, revealing that memory bandwidth—not fixed routing overhead—dominates large-transfer cost; (2) the cFS framework introduces a constant additive overhead of approximately 82.5 μs per task cycle, independent of computational load, remaining below 0.1% of the execution budget at typical 1–10 Hz control rates. System stability is validated through 72 h continuous operation encompassing over 2.5 million task cycles with zero unplanned resets. This work establishes quantitative design guidelines—including memory placement criteria and task granularity thresholds—that provide a reusable technical pathway for deploying reliable, extensible flight software on resource-constrained embedded platforms.
Wu et al. (Sat,) studied this question.