Performance evaluation of InN-based Junctionless FETs under single and double gate architectures

Key Points

• Junctionless FETs demonstrate improved performance metrics, particularly under double gate configurations.
• Key metrics evaluated show significant differences between single and double gate architectures, emphasizing design impact.
• Observational analysis compared performance metrics of InN-based junctionless FETs under different gate structures.
• Highlights the need for ongoing studies to optimize device designs for enhanced electronic applications.