A time-to-digital converter (TDC) based on a middle-stage feedback tapped delay line architecture is proposed to address the demand for precise timing in cross-strip (XS) anode and other photodetection systems that require simultaneous processing of multiple input signals. Implemented 96 TDC channels on Kintex-7 XC7K325T FPGA, the design utilizes the middle-stage feedback delay line to equalize propagation delays and suppress errors, incorporates a ones-counter encoding scheme to improve metastability decoding accuracy, and introduces a FIFO to enhance data throughput at high event rates. The test results indicate that the TDC achieves a time resolution of 11.159 ps and an average RMS precision of 12.90 ps for all TDC channels while consuming only 32 CARRY4 units. Integral nonlinearity (INL) of (−0.349, 0.779) LSB and a differential nonlinearity (DNL) of (−0.947, 1.719) LSB. These results demonstrate the design’s robustness in timing accuracy, linearity, stability, and its suitability for high-precision timestamping in XS anode single-photon detectors. • A Middle-stage feedback delay line TDC architecture is proposed. • Each TDC channel consumes only 32 CARRY4 units. • The TDC has an LSB of 11.159 ps, and an average RMS precision of 12.90 ps.
Zuo et al. (Wed,) studied this question.