Deterministic, microsecond-level timing reproduction in full-system virtualization remains a key challenge for hardware-in-the-loop simulation of timing-sensitive communication buses. This paper presents a virtual time-driven approach that models protocol timing semantics as discrete events on a deterministic virtual timeline, and validates it using MIL-STD-1553B, a representative aerospace bus with strict microsecond-level requirements, as a case study. The MIL-STD-1553B data bus is widely used in aerospace and high-reliability embedded systems, where communication correctness depends not only on message formats but also critically on microsecond-level timing semantics such as message intervals, frame periods, response timeouts, and automatic retries. However, existing Quick Emulator (QEMU)-based virtualization solutions typically rely on host scheduling for timing, making it difficult to maintain determinism under varying loads, which may lead to missed detections or false alarms in timeout/retry behaviors. This paper implements a configurable BU-64843 device model supporting bus controller (BC), remote terminal (RT), and monitor terminal (MT) multi-role switching under a unified framework and completes behavioral modeling of both legacy and enhanced bus controllers covering message scheduling, execution, and exception handling paths. We propose a virtual time-driven precise timing modeling method that explicitly models key timing semantics as discrete events on a virtual timeline. Extensive experiments across 10 timing scenarios demonstrate that our method reduces timing deviation from an average of 8 µs to 65–124 ns (99.1% improvement), achieving deterministic simulation decoupled from host execution speed while meeting the 1 µs minimum resolution requirement. While demonstrated on 1553B, the virtual time-driven method is applicable to other timing-sensitive bus protocols in QEMU-based simulation environments, offering a low-cost, reproducible, and high-precision simulation environment for protocol compliance verification, driver development, and system integration.
Gao et al. (Mon,) studied this question.