This technical note presents a minimal computational stress test on benchmark legitimacy in two-dimensional (2D) transistors under architecture-dependent contact modulation. The note isolates a methodological issue: when electrostatic control affects not only the channel but also the contact region, measured on-state current can include a contact-mediated contribution that inflates apparent performance without implying an equivalent improvement of intrinsic channel transport. Two idealized architectures are compared: one in which gate action affects only the channel, and one in which gate-dependent contact modulation (“contact gating”) is also present. Despite its simplicity, the toy model produces a clear monotonic scaling trend: architecture-dependent performance inflation is moderate in long-channel regimes, increases at intermediate scale, and becomes strong in scaled regimes where contact contributions dominate total resistance. The central result is methodological rather than device-specific. If the access architecture co-produces the quantity it is supposed to assess, then the resulting benchmark cannot be treated as a fully neutral proxy of intrinsic device quality. Under such conditions, performance claims become partially non-transferable across architectures and may exhibit a minimal form of internal non-invertibility, where the same observable current can correspond to different internal decompositions between channel and contacts. This note does not propose new transistor physics and does not aim at predictive device simulation. Its purpose is diagnostic: to provide a compact, reproducible computational illustration of how architecture-induced contact modulation can undermine naive intrinsic-channel interpretations of global performance metrics in 2D transistor evaluation.
Danilo Tavella (Mon,) studied this question.