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This paper presents a 27.5-29.6GHz fractional-N frequency synthesizer using reference and frequency doublers to achieve low in-band and out-of-band phase-noise for 5G mobile communications. The push-push amplifier and 28GHz balun help achieving differential signals with low out-of-band phase noise while consuming low power. A charge pump with gated offset as well as reference doubler help reducing noise-folding effect resulting low in-band phase noise while sampling loop filter helps reducing spurs. The proposed synthesizer has been implemented in 65nm CMOS technology achieving an in-band and out-of-band phase noise of -78dBc/Hz and -126dBc/Hz, respectively while consuming only 33mW. The jitter-power figure-of-merit (FoM) is -231dB which is the highest among the state-of-the-art >20GHz fractional-N PLLs. Reference spurs are less than -80 dBc.
Siriburanon et al. (Tue,) studied this question.
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