Since the advent of large-scale integration, device count and circuit complexity in digital chips have grown exponentially, fueling the digitalization of everyday life. This progress has been enabled by advances in semiconductor fabrication, digital design automation, and system design that exploit increasing compute capability. However, many advances target the processing side, while memory throughput and latency have not scaled commensurately. Massively parallel workloads therefore encounter the memory bottleneck inherent in von Neumann and related architectures, motivating compute-in-Memory (CIM) architectures. In CIM, compute elements are co-integrated with memory cells to alleviate data-movement overheads. This thesis develops an efficient design methodology for CIM architectures, addressing gaps in traditional digital design flows. We evaluate the effectiveness of CIM arrays in genome alignment and deep packet inspection using fabricated silicon. Finally, we develop systems to measure the fabricated designs and assess the impact that these hardware accelerators have on genome alignment in both edge and high-performance contexts. Conventional digital implementation flows start from a hardware description languages (HDL) description, synthesize it to logic gates, and then automatically place and route them, minimizing manual effort but limiting control over cell selection, placement, and regularity. To regain this control, we propose in Chapter 3 a hierarchical approach that defines arrays of standard cells assembled into dense, highly regular arrays 1. We complement this with a template-based, regular routing scheme that provides the additional regularity required because commercial routers cannot route extremely dense designs. For delay-variation-sensitive applications such as time-domain computing, this approach affords the control needed to mitigate the impact of irregular routing. The methodology produces the design collateral needed for standard implementation flows, allowing seamless integration into the flow, as well as the physical layout. Using this approach, we achieve utilizations above 90% and reduce parasitic wiring capacitance by 1.8x compared with an automatically placed-and-routed baseline. While most CIM work targets matrix-vector multiplication, other domains remain underexplored. In genome alignment, a key operation is sorting. Thus, in Chapter 4.2 we implement a CIM-based sorter that performs memory-level maximum computations 2, achieving up to 3.9x lower energy than prior designs due to the data stationarity inherent in CIM. We obtain similar benefits with a finite-automaton accelerator, which we explore in Chapter 4.1. At its core is the lookup of a sparse transition function mapping the current state and input symbol to one or more next states; a pattern well suited to CIM. Our methodology allows the complete automaton function to be implemented in each memory word, yielding an efficient NFA accelerator 3. Regular expressions are commonly used to specify malicious patterns in deep packet inspection and can be mapped to such automata. Using real network-traffic distributions and gating activity with a Bloom filter, the accelerator achieves an energy per input byte of 2.62pJ/B, 4.8x lower than prior designs. We discuss the requirements on the system to measure and validate the designs in Chapter 5.1. Both are fabricated in a 22nm FDSOI technology, providing experimentally validated results in throughput and energy efficiency. Fabrication also enables exploration of constructs not well covered by traditional digital design, such as timing-dependent circuits. In Chapter 5.2 we show that FDSOI technologies are potential targets for trojans to exploit such structures, owing to their wide tunability via the backgate and the lack of an electrical connection between backgate and channel. Using the chips, we demonstrate that hardware trojans, invisible to conventional simulation and analysis, are effective in silicon 4. Because direct validation of such test chips in realistic application scenarios is infeasible, we employ FPGA-based systems to quantify how accelerating base-level alignment 5 in Chapter 5.2 and sorting 6 in Chapter 5.4 affects end-to-end genome alignment. Prior work offers limited assessment of application-level impact and often neglects system constraints. Our system-level evaluations reveal new optimal design points when constraints such as host-communication bandwidth and software offload overheads are considered. In the complete system, the sorter achieves a throughput of 1.3GB/s, almost 4x lower than the ASIC implementation, yet still exceeding main-memory bandwidth.
Christian Dominik Lanius (Thu,) studied this question.