Two-dimensional (2D) semiconductors are promising channel materials for next-generation field-effect transistors (FETs) due to their superior gate control capabilities, dangling-bond-free surfaces, and high mobility. However, it remains challenging to integrate ultrathin and uniform high-k dielectrics on 2D semiconductors to fabricate FETs with large gate capacitance and clean interfaces. Here, we report a high-k dielectric TaOx prepared via UV ozone oxidation of layered tantalum disulfide (TaS2), with a high effective dielectric constant (εr) of ∼28 and a breakdown field of ∼8 MV/cm. We integrated the TaOx dielectric with 2D semiconductors through van der Waals assembly, exhibiting small hysteresis (10 mV), a high current on/off ratio approaching 107, a steep subthreshold swing of 64 mV/dec, and a low interface trap density Dit of ∼6.8 × 1011 cm−2 eV−1. By integrating n-type MoS2 and p-type WSe2 transistors with van der Waals dielectric TaOx, we have realized logic circuits with low static power consumption capable of performing NOT, NAND, and NOR operations. Notably, the logic inverter (NOT gate) exhibits a static voltage gain as high as 260. Our dielectric fabrication strategy can be used to integrate 2D materials and amorphous oxide dielectrics, thus offering a promising approach for the development of high-performance low-power electronics.
Tong et al. (Mon,) studied this question.