What question did this study set out to answer?

The aim is to optimize leakage power in digital circuits through innovative design techniques.

April 18, 2026Open Access

Leakage Power Optimization Using Adaptive Body Bias/Dynamic Body Bias with Graph Deep Neural Networks and Reinforcement Learning

Key Points

The aim is to optimize leakage power in digital circuits through innovative design techniques.
Implemented Adaptive Body Bias and Dynamic Body Bias methods
Utilized clock gating, power gating, and transistor optimization
Applied graph deep neural networks and reinforcement learning for optimization
Achieved significant reductions in leakage power across tested circuits
Improved overall energy efficiency demonstrated through simulations
Validated techniques contributing to lower operational costs and enhanced performance

Abstract

This work presents a study on low power VLSI design techniques aimed at reducing power consumption in digital circuits. The paper discusses methods such as Adaptive Body Bias/Dynamic Body Bias, clock gating, power gating, and transistor optimization to improve energy efficiency. The uploaded file contains the full manuscript in PDF format. This work is shared as a preprint.

Leakage Power Optimization Using Adaptive Body Bias/Dynamic Body Bias with Graph Deep Neural Networks and Reinforcement Learning

Key Points

Abstract

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