Key points are not available for this paper at this time.
This work proposes process/resistance variation-insensitive read schemes for embedded RRAM to achieve fast read speeds with high yields. An embedded mega-bit scale (4Mb), single-level-cell (SLC) RRAM macro with sub-8ns read-write random access time is presented. Multi-level-cell (MLC) operation with 160ns write-verify operation is demonstrated.
Sheu et al. (2011) studied this question.