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A 64-Mb dynamic RAM (DRAM) has been developed with a meshed power line (MPL) and a quasi-distributed sense-amplifier driver (qDSAD) scheme. It realizes high speed, t/sub RAS/=50 ns (typical) at V/sub cc/=3.3 V, and 16-b input/output (I/O). This MPL+qDSAD scheme can reduce sensing delay caused by the metal layer resistance. Furthermore, to suppress crosstalk noise, a V/sub SS/ shield peripheral layout scheme has been introduced, which also widens power line widths. This 64-Mb DRAM was fabricated with 0.4- mu m CMOS technology using KrF excimer laser lithography. A newly developed memory cell structure, the tunnel-shaped stacked-capacitor cell (TSSC), was adapted to this 64-Mb DRAM.>
Yamada et al. (Tue,) studied this question.
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