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Integrated circuits, printed circuits boards, and multi-board systems are becoming increasingly complex to test. A major obstacle is test access, which would be eased by effective standards for the communication between devices-under-test (DUTs) and the test manager. Currently, the Internal Joint Test Access Group (IJTAG) work at micro-level on a standard for interfacing embedded on-chip instruments while the System JTAG (SJTAG) work at macro-level on a standard for system-level test management that connects IJTAG compatible instruments with the system test manager. In this paper we discuss requirements on a test protocol to be used in an SJTAG/ IJTAG environment. We have from a number of use scenarios made an analysis and defined protocol requirements. We have taken the Standard Test and Programming Language (STAPL), which is built around a player (interpreter), and defined required extensions. The extensions have been implemented in an extended version of STAPL and we have made experiments with a PC acting as test controller and an FPGA being the DUT.
Carlsson et al. (Mon,) studied this question.