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The ultra-high frequency (UHF) tag IC's main part of the power management unit (PMU) design technique is presented. The technique is a step-by-step algorithm for designing a PMU and consists of five interrelated stages. At the first stage, the requirements for the parameters of the PMU (output voltage, output DC power, efficiency, output capacitor capacity) and the Q-factor of the tag analog front-end are determinates. At the second stage, the design of an electrical circuit of a voltage multiplier (VM) is carried out. VM is required to convert the voltage of the input radio frequency (RF) signal into an DC voltage. During the third stage, the design of the electrical circuit of the DC voltage limiter is carried out, which is necessary to reduce the output voltage of VM to a safe level. The result of stage 4 is an electrical circuit of surge protection designed to provide the required level of immunity of the tag IC to the effects of electrostatic discharge and a high-power RF signal. As part of the final stage, the evaluation and alignment with the required Q-factor value of the tag IC analog front-end is carried out. The proposed technique can be used for the development of domestic UHF tag ICs (ISO 18000-6C, GJB 7377.1, etc.) based on CMOS technological processes, including ICs designed for radio frequency identification of critical infrastructure objects. Using the presented technique, the design of a PMU with an estimated efficiency value of 70%, an estimated Q-factor of the analog front-end of less than 15 at an RF input signal power of -12.7 dBm was performed.
Sotskov et al. (Sat,) studied this question.