Performance of Well-Organized VLSI Architecture for Three Operand Binary Adder

The adder is represented as block; the Three-operand binary adder is represented as block0, the Han-Carlson adder is represented as block1, the Carry save adder is represented as block2 & the Proposed adder is represented as block3. Block0 is a pivotal functional tool in numerous cryptography and bit generator (PRBG) techniques, particularly in implementing modular arithmetic. Regarding three-operand addition, the most commonly utilized approach is the carry-save adder (CSA). Nevertheless, the ripple-carry phase inherent in the CSA introduces a notable O(n) propagation delay. Within the three-operand addition, an alternate approach entails employing block 1. This method provides a significant decrease in critical path time. A new design has been created to perform three-operand binary addition, presenting an efficient architecture combining pre-compute bitwise addition with block2 logic. This integration yields a decreased block latency of O(log2 n), accompanied by lower power consumption and a smaller spatial footprint. The proposed design has been implemented using a commercially available 180nm CMOS technology library and validated on an FPGA device to ensure its functionality. Compared to the HCA adder, the suggested design exhibits a smaller footprint, lower power dispersion, and shorter quiescence. Additionally, in terms of area, Delay Power, and leakage Power, the proposed adder surpasses current three-operand adder techniques. The proposed adder exhibits a leakage power of 1667.9n Wand a dynamic power of 17105.504 nW.