What question did this study set out to answer?

To enhance VLSI floor planning efficiency and effectiveness using genetic algorithms for both 2D and 3D designs.

February 8, 2026Open Access

Optimized VLSI floor planning using genetic algorithm

Key Points

To enhance VLSI floor planning efficiency and effectiveness using genetic algorithms for both 2D and 3D designs.
Utilized a genetic algorithm to represent floorplans as chromosomes.
Employed selection, crossover, and mutation for iterative improvements.
Conducted experimental comparisons against traditional methods such as SA, DMT, and PSO.
Achieved higher efficiency in block placement compared to traditional methods.
Reduced wirelength significantly throughout the experiments.
Decreased computation time, confirming GA as effective for large-scale problems.

Abstract

VLSI floorplanning is a fundamental step in physical design automation that directly impacts chip performance, power consumption, and area utilization. Classic optimization methods include SA, DMT, and PSO; their convergence speeds are rather poor, especially for large-scale designs. This paper addresses both 2D and 3D floorplanning using a Genetic Algorithm (GA). GA represents the floorplans as chromosomes and applies selection, crossover, and mutation to improve block placement iteratively. Experimental comparisons, presented in a two-row tabular format, show that the GA achieves higher efficiency in block placement, wirelength reduction, and computation time compared to SA, DMT, and PSO. The results confirm that GA is indeed one of the effective solutions for large-scale floor planning problems.

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