The memory demands of large-scale deep neural networks (DNNs) require synaptic weight values to be stored and updated in off-chip memory, such as dynamic random-access memory, which reduces energy efficiency and increases training time. Monolithic crossbar or pseudo-crossbar arrays using analog non-volatile memories, which can store and update weights on-chip, present an opportunity to efficiently accelerate DNN training. In this article, we present on-chip training and inference of a neural network using an ULTRARAM memory device-based synaptic array and complementary metal–oxide–semiconductor (CMOS) peripheral circuits. ULTRARAM is a promising emerging memory exhibiting high endurance (107 P/E cycles), ultrahigh retention (1000 years), and ultralow switching energy per unit area. A physics-based compact model of ULTRARAM memory device has been proposed to capture the real-time trapping/de-trapping of charges in the floating gate and utilized for the synapse simulations. A circuit-level macro-model is employed to evaluate and benchmark the on-chip learning performance in terms of area, latency, energy, and accuracy of an ULTRARAM synaptic core. In comparison with CMOS-based design, it demonstrates an overall improvement in area and energy by 1.8× and 1.52×, respectively, with 91% of training accuracy.
Kumar et al. (Mon,) studied this question.