ABSTRACT This research leverages advanced monolithic silicon‐photonics integrated‐circuit manufacturing capabilities to realize system‐on‐chip photonic‐computing‐based linear‐algebra accelerators for a wide range of applications in artificial intelligence, machine learning, and multiple‐input multiple‐output wireless technology. With holistic codesign in both photonic and electronic domains, strategic electrical‐to‐optical signal conversion, a differential intensity‐modulation technique, and a dual rail‐to‐rail photodetection architecture, the monolithic photonic‐electronic test chip of a sign‐sign dot‐product accelerator achieves 8.92‐Gb/s/MAC computation throughput with 2.22‐pJ/b/MAC energy consumption for next‐generation large‐scale linear‐algebra computing hardware targeting higher than one TMAC/s/mm 2 computation density with only tens of fJ/MAC energy consumption.
Chaudhury et al. (Wed,) studied this question.