FPGA-Based Implementations of Biometric Recognition: A Review

Field-programmable gate arrays (FPGAs) are increasingly used to bring biometric recognition from cloud- or GPU-centric deployments to resource-constrained edge devices where latency, power, and privacy are critical. This paper surveys recent (2021–2025) FPGA and FPGA-SoC implementations across five widely deployed modalities: face, fingerprint, iris, speaker (voiceprint), and finger vein. For each modality, we summarize representative implementations and the performance figures commonly reported in the literature (e.g., accuracy or EER, latency/throughput, resource usage, and power), highlighting the algorithm–hardware co-design choices that enable real-time operation. Across modalities, successful designs repeatedly employ streaming/dataflow architectures, aggressive quantization and fixed-point arithmetic, reuse-aware buffering, and heterogeneous CPU–FPGA partitioning, often supported by high-level synthesis and vendor deep learning IP. Beyond throughput, we discuss how FPGAs facilitate privacy-preserving on-device processing and can integrate template protection and presentation attack detection within the same fabric. Finally, we identify open challenges related to scalability to larger models, memory-bandwidth constraints, and design productivity, and outline research directions enabled by emerging adaptive FPGA architectures and more automated toolflows. Overall, the surveyed evidence indicates that FPGAs are a compelling platform for deterministic, energy-efficient, and secure biometric inference at the sensor edge.