An Improved Sobel Edge Algorithm and FPGA Implementation

In this paper,the traditional Sobel edge detection algorithm for the calculation of the gradient of less template and the multiplication operation is time-consuming, resulting in complex image edge detection is not clear and the slow processing speed,this paper puts forward a method to increase the gradient template and change the way the new multiplication gradient. Sobel edge detection algorithm the new gradient calculation method based on the FPGA technology, parallel processing capability and high reliability, flexibility and reconfigurability of good features using the FPGA chip to complete the design of improved Sobel edge detection algorithm, to solve the traditional Sobel algorithm is not clear enough and algorithm processing speed problem for complex image edge detection. This design uses Verilog HDL language to design and implement each module.The Quartus II 8.0 software is used to simulate the model and download it to the DE2 development board with Altera EP2C35F672C6 as the target chip, and finally achieves the design requirements.