Negative-bias temperature instability in AlSiO/p-type GaN metal-oxide-semiconductor field-effect transistors with ultrathin AlN interfacial layer

A technique for inserting a thin crystalline AlN interfacial layer (AlN-IL) at the oxide/p-type GaN interface is investigated to enhance the channel mobility in GaN metal-oxide-semiconductor field-effect transistors (MOSFETs). In this study, the negative-bias temperature instability (NBTI) for AlSiO/p-type GaN MOSFETs with and without an AlN-IL is discussed. Capacitance–voltage analyses revealed a high density of interface states at energy levels of 1 and 0.8 eV above the valence-band maximum for GaN in the MOSFETs with and without an AlN-IL, respectively. In the MOSFET without an AlN-IL, the threshold voltage (Vth) rapidly shifted to negative and subsequently remained unchanged, even when a stress voltage was applied. In addition, the shift was reduced at high temperatures, likely because of thermal emission of holes from the interface states. By contrast, the Vth shift for the MOSFET with an AlN-IL gradually increased with increasing applied bias stress time. When the AlN-IL thickness was reduced to 0.8 nm, the Vth shift decreased compared with that for the MOSFET without an AlN-IL. However, the negative Vth shift was enhanced and proportional to the logarithm of the stress time at a temperature of 100 °C, indicating a tunneling process. The increase in the Vth shift at 100 °C is likely caused by hole tunneling to the band discontinuity at AlSiO/AlN through the polarization-field-induced triangular potential in the AlN-IL. Thus, engineering of band alignment is a key for NBTI control in an AlSiO/AlN/p-type GaN MOSFET with high channel mobility.