Design consideration for full well capacity and charge transfer efficiency of a CCD-in-CMOS imager pixel: TCAD study

In recent years, CCD-in-CMOS time delayed integration (TDI) image sensors are becoming increasingly popular for many small satellite missions to assure fast and affordable access to space for Low Earth Observation. Imec first introduced its monolithic CCD-in-CMOS technology at IEDM 2014. It combines the benefits of a classical CCD TDI with the advantages of CMOS System-On-a-Chip (SoC) design. Imec's CCD-in-CMOS technology is continuously being tuned to reach high pixel performance. This paper presents Technology Computer Aided Design (TCAD)-based design methodology of a CCD-in-CMOS imager pixel. This pixel design methodology includes test structure based TCAD simulation approach to design CCD-in-CMOS pixel by extracting design conditions and criteria to achieve CCD performance specifications. In this methodology, the proposed design technique discloses a way to realize CCD functionality integration in the charge domain with a view to optimizing the critical parameters such as full well capacity (FWC) and charge transfer efficiency (CTE). As a part of this design consideration, we studied transient behavior of charge transfer efficiency (CTE). As the charge transfer process within pixels differs from the conditions when charge is being dumped from the output summing well (OSW) to the floating diffusion (FD), these two cases are considered separately. Ideal clocks with different slews are used for the pixel-to-pixel transfer study, whereas they have been replaced with more realistic exponential curves for the output charge drain simulations, allowing a further refinement of the results. Although this work was originally done for CCD-in-CMOS TDI pixel design, this is in no way specific to the only TDI CCD-in-CMOS. Rather, the proposed methodology is applicable to all types of CCD pixel-design.