(Keynote) High-Performance Carbon Nanotube Transistors for Logic Platform

Low-dimensional 1D and 2D materials hold promise as candidate channel materials for highly scaled and high-performance transistors beyond the limits of silicon-based transistors. This talk will first motivate transistors built on low-dimensional channels due to the significant speed, energy efficiency, and transistor density benefits enabled by their electronic and physical properties. This talk will focus on 1D carbon nanotube (CNT) semiconductors and describe the advanced device component process modules that have been demonstrated, explaining both the fundamental mechanisms of operation and device-level performance objectives. Single-CNT FET experimental studies give insight into the quality of (1) low resistance N- and P- contacts down to 10 nm contact length, (2) high-capacitance gate dielectrics optimized for deposition on SP2 carbon surfaces, and (3) controlled N- and P- remote dielectric doping. To achieve high current density each transistor must contain multiple CNTs, therefore we will review state-of-the-art strategies to assemble densely aligned arrays of CNT with controlled CNT spacing between 2-10 nm and uniform electronic bandgap. The final portion of the talk will highlight recent advances from our team and others to integrate the best device components together to demonstrate high-performance carbon nanotube MOSFETs. We will elaborate on the remaining challenges and provide a summary of device design tradeoffs that will help guide future studies. We are grateful for support and collaboration from TSMC Corporate Research, DoD, Stanford SystemX Alliance, Stanford Nanofabrication Facility, Stanford Nano Shared Facility, and the University of California at San Diego.