Optimized Sequential State Encoding Methods for Finite-State Machines in Field-Programmable Gate Array Implementations

A Finite-State Machine (FSM) model is frequently employed to represent the behavior of sequential circuits. In the optimal design of these circuits, it is crucial to enhance FSM characteristics such as area (implementation cost), performance (operating frequency), and power consumption. This paper proposes sequential state encoding methods that aim to reduce the area and enhance the performance of FSMs. The methods involve sequentially selecting FSM states for encoding and determining the most appropriate code for each selected state. Several state and code selection modes are introduced, allowing for consideration of the relationships between states, the number of incoming and outgoing transitions, and the number of input variables initiating transitions to each state. The code selection process takes into account the architectural features of the electronic device in which the FSM is implemented, while some code selection modes are introduced to optimize both the area and performance of the FSM. The experimental results demonstrate that the proposed approach yields, on average, a reduction in the FSM area by 19.7% (in some instances, up to twofold reduction), along with an average performance increase of 21.2% (in certain cases, up to 69.3%), compared to the Sequential mode of the Quartus system.