VeriPy: A Python-Powered Framework for Parsing Verilog HDL and High-Level Behavioral Analysis of Hardware

This work introduces VeriPy, a Python-based frame-work for parsing Verilog descriptions, that facilitates the extraction of the behavioral functionality of the hardware and creates a high-level controlled data flow graph (CDFG), removing architectural details and timing information. This raises the level of abstraction, which makes the functional analysis of the hardware easier. The proposed framework follows a bottom up module based parsing approach and utilizes transfer learning to create efficient and easily comprehensible CDFG. VeriPy provide a flexible front-end platform f or t he modernization o f legacy RTL designs by converting them into synthesizable high-level languages like C, C++ or SystemC which in turn can be re-synthesized with new constrains and target technologies back to RTL through High-Level Synthesis (HLS). Our framework also performs different optimizations like identifying redundant operation, and can help to identify potential hardware security threats like Hardware (HW) Trojans in third party RTL IPs (3PIP). Experimental results show the efficiency o four frame-work warning users about potential HW Trojans.