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With datacenters introducing 800G/1.6T switches and emerging artificial intelligence accelerator ASICs demanding higher aggregate I/O bandwidth, 224Gb/s PAM-4 transceivers are expected to supersede today's dominant 112Gb/s SERDES. Such transceivers must double analog I/O bandwidth to 56GHz while maintaining or exceeding the previous generation's energy efficiency. This requires substantial improvements in the data and clock paths. With the baud rate doubled, channel losses exceeding 35dB must be addressed by higher order digital equalizers and optional maximum likelihood sequence detection (MLSD). The growing digital signal processing (DSP) complexity is compensated by the logic gate density offered by advanced FinFET nodes. This paper presents solutions for a 224Gb/s receiver frontend and transmitter backend and their associated clock paths.
Pfaff et al. (Sun,) studied this question.