Our project, "Optimized Wallace Tree Multiplier Using High-Order Compressors," focuses on enhancing the performance of multipliers in digital systems and signal processing applications. Adders and multipliers play a major role in designing complex circuits, but traditional multipliers consume significant area, delay, and power. To improve multiplier efficiency, multiple architectures have been designed. In this project, a Wallace tree multiplier is proposed to enhance speed using compressors. The key focus is on partial product reduction, which significantly impacts multiplier performance. Initially, 4:2 compressors are used for reduction. However, as the input bit length increases, complexity grows, making the multiplication process more time- consuming. To address this, multi-input compressors are used to further shorten partial products. In the proposed design, a higher-order 7:3 compressor is incorporated to minimize delay, achieving better performance compared to previous multiplier architectures
Priya et al. (Thu,) studied this question.