This paper introduces substrate confinement within the MID/QC framework, showing how corridor narrowing and gating compression induce logic bottlenecks and feasibility saturation. Reaction throughput stalls as corridor width collapses and gating thresholds tighten. The manuscript explains how substrates host confinement zones and saturation fields, reframing saturation as a substrate-native bottleneck mechanism. Engineered substrates can throttle logic propagation and overload feasibility encoding through geometric compression.
Chadwick Rasque (Fri,) studied this question.