What question did this study set out to answer?

To characterize the fidelity and performance of controlled-NOT and controlled-phase gates on superconducting quantum processors.

February 11, 2026Open Access

Characterizing conditional quantum dynamics on superconducting quantum processors

Key Points

To characterize the fidelity and performance of controlled-NOT and controlled-phase gates on superconducting quantum processors.
Implemented controlled-NOT and controlled-phase gates using a superconducting processor.
Conducted full quantum process tomography and direct state measurements.
Benchmarked gates against a noise-free quantum simulator to isolate errors.
Controlled-NOT gate achieved average process fidelity of 93.02%.
Controlled-NOT gate prepared the target state with a probability of 92.40%.
Controlled-phase gate achieved a process fidelity of 92.59% and superior state-preparation fidelity of 97.08%.
Compiled controlled-phase gate outperformed native controlled-NOT gate by 4.68 percentage points in state preservation.

Abstract

Abstract The pursuit of practical quantum computation relies on the precise implementation and characterization of high-fidelity entangling gates. We present a detailed experimental characterization of the controlled-NOT (CX) and controlled-phase (CZ) gates on a noisy intermediate-scale quantum (NISQ) superconducting processor using full quantum process tomography and direct state measurements. The gates were benchmarked against a noise-free quantum simulator to isolate hardware-induced errors. The CX gate, implemented as a native gate, achieved an average process fidelity of Fₚ^ {CX} = 93. 02\% F p CX = 93. 02 % and correctly prepared the target state with P₀₀^ {CX} = 92. 40\% P 00 CX = 92. 40 % probability. The CZ gate, decomposed into a sequence of single-qubit and CX gates, achieved Fₚ^ {CZ} = 92. 59\% F p CZ = 92. 59 % with superior state-preparation fidelity of P₀₀^ {CZ} = 97. 08\% P 00 CZ = 97. 08 %. Remarkably, the compiled CZ gate outperformed the native CX gate in state preservation by 4. 68-percentage points, demonstrating the effectiveness of hardware-aware compilation. Our analysis provides a comprehensive benchmark of these essential gates, revealing that compilation strategy can be as crucial as native hardware performance for reliable quantum circuit execution in the NISQ era.

Bookmark

View Full Paper