The growing need for energy-efficient and flexible computing systems has led to increased interest in coarse-grain reconfigurable architectures (CGRAs). Although CGRAs offer adaptability and high performance, many existing designs prioritize performance improvements over energy efficiency. In this work, we introduce a new reconfigurable architecture called Blocks, designed with a strong focus on reducing energy consumption while maintaining flexibility and performance. Blocks adopt a novel design approach by separating control and data communication into two independent circuit-switched networks. This separation allows the system to dynamically configure application-specific VLIW-SIMD processors on a reconfigurable fabric, improving overall efficiency. By tailoring the hardware to the needs of each application, Blocks minimizes unnecessary data movement and switching activity, leading to significant energy savings. To evaluate its effectiveness, Blocks is compared with four reference architectures: a VLIW processor, an SIMD processor, a commercial low-power microprocessor, and a conventional CGRA, all implemented in commercial 40-nm CMOS technology including memory components. The results show that Blocks achieves substantial energy reductions—2.05× over VLIW, 1.84× over SIMD, 8.01× over the low-power microprocessor, and 1.22× over the traditional CGRA—while delivering equal or better performance per area. These findings demonstrate that Blocks provides an effective balance between energy efficiency, flexibility, and performance.
Sreenivasulu et al. (Thu,) studied this question.