Efficient Design of Reversible Adder and Multiplier Using Peres Gates

This paper details the approach to the efficient design and optimization of a reversible adder and multiplier utilizing Peres gates, which is a three-input, three-output gate. Peres gates are recognized for their universality and energy-efficient properties and present an intriguing option for constructing reversible circuits. Reversible logic is characterized by its ability to uniquely determine input states from output states. The design methodology involves a cascading arrangement of Peres gates, each performing a reversible XOR operation on corresponding bits of the input numbers and the carry-out from the preceding stage. This paper presents a detailed schematic representation, simulation results, and analysis of the proposed designs of different adders and multipliers, showcasing their potential for reversible applications. The integration of Peres gates in the adder and multiplier design signifies a step forward in the exploration of reversible logic circuits and their applications in contemporary computing paradigms. The overall hardware reduction is the main achievement of this research in terms of quantum cost.