Reduction of hysteresis in MoS 2 transistors using pulsed voltage measurements

Abstract Transistors based on two-dimensional (2D) materials often exhibit hysteresis in their electrical measurements, i.e. a dependence of measured current on voltage sweep direction due to charge trapping. Here we demonstrate a simple pulsed measurement technique which reduces this hysteretic behavior, enabling more accurate characterization of 2D transistors. We compare hysteresis and charge trapping in four types of devices fabricated from both exfoliated and synthetic MoS 2 , with SiO 2 and HfO 2 insulators, using DC and pulsed voltage measurements at different temperatures. Applying modest voltage pulses (~1 ms) on the gate significantly reduces charge trapping and results in the elimination of over 80% of hysteresis for all devices. At shorter pulse widths (~1 µ s), up to 99% of hysteresis is reduced for some devices. Our measurements enable the extraction of a unique value of field-effect mobility, regardless of voltage sweep direction, unlike measurements that rely on forward or backward DC measurements. This simple and reproducible technique is useful for studying the intrinsic properties of 2D transistors, and can be similarly applied to other nanoscale and emerging devices where charge trapping is of concern.