With increasing pin counts in chip packages and the widespread adoption of multiple power domains, the complexity and cost of package design have greatly increased. To maintain power integrity, a large copper-filled area is used for power delivery in package substrate design. Since multiple power domains share the same substrate metal layer, the layer must be partitioned into several non-overlapping sub-regions, which engineers manually handcraft. In this paper, we propose an automated framework for power plane layout partitioning and optimization. The framework comprises two major stages: topology generation and polygon generation. In the topology generation stage, we propose pin grouping, edge selection, and edge-cost adjustment methods to efficiently generate the topology of each power domain within the same metal layer. In the polygon generation stage, pseudo-node insertion is first applied to generate initial metal polygons, and a bisection method is then iteratively performed to optimize the shapes, areas, and resistances of the multiple power domains simultaneously. The experimental results demonstrate that our framework efficiently generates power plane layouts that account for static power integrity (DC IR-drop) and can serve as a basis for future transient analysis.
Lin et al. (Thu,) studied this question.