SLIC3: The synchronised/Limit Cycle Conductance Controller

A derivative of the LC 3 (Limit Cycle Conductance Controller) principle, the SLIC 3 overcomes one of the only disadvantages of the existing LC 3 principle in that it is synchronisable and thus multiphase operation of parallel pcwer sharing modules is achieved. Unlike many of the current range of synchronised current controlled regulators, the SLIC 3 , in the absence of a synchronised signal, will revert to LC 3 mode of operation and thus the synchronisation source is not an essential function of the regulator principle, hence no complex, redundant multiphase clock signal generators are required. It is intended to present in this paper, a detailed laboratory design of the SLIC 3 incorporating Power FET's and many detailed design features which have been developed since the original LC 3 publication in 1977.