Large Scale Integration of MOS Complex Logic: A Layout Method

Large scale integration of complex logic is generally assumed to be a compromise between two conflicting cost factors, i.e., reduced design time through layout standardization, and increased yield through high circuit density, A unique but rather simple layout method is described that combines layout standardization with high circuit density generally expected from customized layout. At the same time, the design of the personality (the desired interconnection pattern) is simplified, while using a single layer of metallization. The method has been applied to complex logic using MOS NOR circuits.