Effect of wire delay on the design of prefix adders in deep-submicron technology

This paper investigates the wire delay effect on the design of prefix adders when the technology moves from 250 nm to 70 nm. The simulation is based on parameters from NTRS'97 and uses an analytical wire delay model that considers the fanout effect and the distributive nature of wire capacitance and resistance. Simulation results show that wire delay exceeds logic delay and dominates the critical path delay of prefix adders in many cases. For a given technology, the wire delay contribution increases steadily as the adder width increases. As the feature size decreases, however, the wire delay contribution decreases slowly. The simulation data also imply that there is little need to consider wire resistance. On the other hand, the effect of wire coupling capacitance plays a critical role in prefix adders' performance.