The Architectural Elements of a Symmetric Fault-Tolerant Multiprocessor

A hybrid-redundant multiprocessor is proposed in which each processing unit and each memory module is triplicated for purposes of error detection and momentary error masking Reconfiguration allows spare units to replace failed units and allows surviving units to regroup after spares have been exhausted. An arbitrary number of processing units and memory modules can be accommodated. A hybrid-redundant bus system interconnects the processors and memories, where the initial redundancy of the buses is a design parameter. A specialized circuit called a bus guardian unit (BGU) is employed in numerous places to control reconfiguration and testing in such a way as to eliminate susceptibility to failure events that occur in one module at a time. Considerable emphasis is placed on dynamic testing. This approach is briefly compared to other fault-tolerant computer systems.