An Analog Front End ASIC for Cardiac Electrical Impedance Tomography

In this paper, an end-to-end CMOS application specific integrated circuit (ASIC) for readout channel in a cardiac electrical impedance tomography system is presented. The ASIC consists of an integrated current driver for current injection, an instrumentation amplifier, variable gain amplifier at the analog front end for voltage readout from electrodes, and an on-chip 10-bit successive approximation register analog to digital converter with serial peripheral interface. The ASIC is fabricated in the CMOS 0. 18 m process with a supply voltage of 3. 3 V. Amplitude and phase extraction of the voltages is performed in the digital domain with a matched filter. A fully integrated solution for use in multiple electrode system is demonstrated. The readout chain in the ASIC achieves a minimum signal-to-noise ratio of 71 dB over the frequency range of 500 Hz-700 kHz, while maintaining an average accuracy of 99. 7 \%. Frame rates of 21 frames per second for a 32 electrode system is feasible, and the ASIC has an overall power consumption of 11. 8 mW.