A GHz IA-32 architecture microprocessor implemented on 0.18 μm technology with aluminum interconnect

A 28M transistor 0.18 /spl mu/m CMOS microprocessor uses aluminum interconnect to defer the cost of copper technology conversion by one process generation with little design-effort impact. The implementation is an architectural superset of a previous Pentium (R) III Processor implemented in 0.25 /spl mu/m CMOS. Feature additions include: placement of 256 k L2 advanced transfer cache on die with re-optimized data width and latency. Speed step dual-voltage VCC support for enhanced mobile products. The bandwidth to L2 cache is increased to 16 GB/s at 1.0 GHz utilizing a 256 bit data bus with >4x reduction in latency. The L2 architecture is easily scalable to enable variations of the design with different cache sizes. Advanced system buffering in the memory subsystem increases utilization of system bus bandwidth. System bus bandwidth is 1.066 GB/s utilizing a 64 b data bus operating at 133 MHz. The chip runs at 1 GHz core frequency at room temperature and nominal voltage. This performance milestone is achieved by enabling full utilization of 0.18 /spl mu/m transistor performance with rigorous attention to wire engineering. This did not require the use of either copper interconnect or dual Vt.