November 13, 2002

Diagnosing combinational logic designs using the single location at-a-time (SLAT) paradigm

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Abstract

A new way of diagnosing ICs that fail logic tests is described. It can handle bridging fault, opens, transition faults and many more complex defects as easily and as accurately as regular stuck-at faults.

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Bartenstein et al. (Wed,) studied this question.

synapsesocial.com/papers/6a22db783e37827e79207936 https://doi.org/https://doi.org/10.1109/test.2001.966644