Implementation of steerable spatiotemporal image filters on the focal plane

This paper presents an architectural overview of a pseudogeneral image processor (GIP) chip for realizing steerable spatial and temporal filters at the focal-plane. The convolution of the image with programmable kernels is realized with area-efficient and real-time circuits. The chip's architecture allows photoreceptor cells to be small and densely packed by performing all analog computations on the read-out, away from the array. The size, configuration, and coefficients of the kernels can be varied on the fly. In addition to the raw intensity image, the chip outputs four processed images in parallel. The convolution is implemented with a digitally programmable analog processor, resulting in very low-power consumption at high-computation rates. A 16/spl times/16 pixels prototype of the GIP has been fabricated in a standard 1.2-/spl mu/m CMOS process and its spatiotemporal capabilities have been successfully tested. The chip exhibits 1 GOPS/mW at 20 kft/s while computing four spatiotemporal convolutions in parallel.