A hardware-efficient Berkeley gate for superconducting quantum processors

Abstract The Berkeley gate is a high-performance, two-qubit entangling operation with particular potential for quantum error correction and fault-tolerant protocols. However, harnessing this potential on current noisy intermediate-scale quantum (NISQ) processors, requires efficient compilation and robust performance under realistic noise conditions. In this work, we demonstrate a hardware-efficient implementation of the Berkeley gate on a superconducting quantum processor. Using quantum process tomography (QPT), we experimentally characterize its performance and benchmark it against a noiseless quantum simulator to evaluate its practical reliability in the NISQ era. Experimental measurements confirm the gate’s correct logical action, producing the target partially entangled state with a subspace confinement probability of P ₒₔ₂₂^ {hardware} 95. 96\% on real quantum hardware compared to 100% in quantum simulation. Results from QPT experiments show a simulated process fidelity of F ₏ₑ₎₂₄ₒₒ^ {sim} = 98. 23\%, while the experimental process fidelity on hardware is F ₏ₑ₎₂₄ₒₒ^ {hardware} = 91. 76\%. The observed discrepancy is analyzed in the context of device-specific noise sources, including qubit relaxation, dephasing, and state preparation and measurement (SPAM) errors. Our work provides a concrete fidelity benchmark for the Berkeley gate on superconducting hardware and quantify the impact of realistic noise on a non-trivial two-qubit operation, supporting its use in near-term algorithmic and error-correction applications.