Hybrid Interconnect Infrastructure for Inter-Chiplet Communication in Wafer-Scale Systems

The semiconductor industry is shifting towards intimate heterogeneous integration of small chips/dies (chiplets/dielets), rather than focusing on large systems-on-chip (SoCs). The chiplet paradigm promotes heterogeneity, scalability, lower non-recurring engineering cost, shorter time-to-market, and simplified testing. That said, important design and manufacturing challenges must be addressed for chiplet-based platforms to take center stage in semiconductor design. Efficient, scalable, and CMOS-compatible interconnect infrastructure, to ensure signal integrity for inter-chiplet communication, is a key design challenge for chiplet-based systems. This challenge is especially important in wafer-scale systems, where efficient package-level long-range communication is critical.A hybrid inter-chiplet interconnect infrastructure for large-scale chiplet-based systems is introduced in this paper. The proposed infrastructure utilizes electrical and silicon photonics-based interconnects for, respectively, short- and long-range inter-chiplet communication. Architecture and characterization of the proposed infrastructure are discussed. Simulation results confirm that the proposed interconnect infrastructure exhibits an energy consumption of 150, 240, and 305 fJ/bit for, respectively, short-, medium-, and long-range inter-chiplet communication on a wafer-scale integration platform. The proposed hybrid communication system significantly outperforms state-of-the-art electrical medium- and long-range communication with an energy requirement in the range of 0.8-1.17 pJ/bit.