Parallel Flagged Fault‐tolerant Error Correction for Stabilizer Codes of Distance 5

Abstract Flagged fault‐tolerant error correction schemes have attracted a lot of attention for their low qubit overhead, but usually require a high circuit depth. One way to reduce the depth is to develop parallel flagged syndrome extraction circuits. This study investigates parallel syndrome extraction circuits for Calderbank‐Shor‐Steane codes with distance 5. A simple algorithm for finding parallel flagged syndrome extraction circuits is provided. Using this algorithm, the parallel flagged circuits of the [17,1,5] and [19,1,5] color codes are constructed precisely. The error pseudo‐thresholds for code schemes are also precisely simulated and calculated. The parallel scheme in this study, based on the [17,1,5] and [19,1,5] color codes, outperforms traditional flagged schemes, particularly when the idle location error rate is high.