ABSTRACT A harmonic‐included canonical section‐wise piecewise linear (CSWPL) model with both bias and frequency information is presented in this study. This new model is verified by means of fundamental and harmonic load‐pull simulation data for a 10‐W gallium nitride (GaN) packaged transistor considering a wide range of input power. According to the proposed model, the harmonic behavior of the device under test (DUT) can be captured more accurately than what is currently available in the existing fundamental‐only CSWPL model, which is very helpful for the designers of power amplifiers (PAs). Further, the proposed model is implemented in Keysight advanced design system (ADS) simulator by using a frequency‐domain defined device (FDD), which is then applied to the design of a single‐ended broadband PA. In accordance with the results achieved, the GaN‐based PA has a power added efficiency (PAE) greater than 60% and an output power greater than 40 dBm over the frequency range of 2 to 3 GHz. A very good match exists between the simulation results of the proposed model and the actual measurements of real PAs, which demonstrates the suitability of the presented model for practical PA applications.
Zhou et al. (Sun,) studied this question.