Materials Design Principles for Large Memory Windows: Coercive Voltage Engineering in Ferroelectric– Dielectric Heterostructures (Adv. Electron. Mater. 8/2026)

Ferroelectric–Dielectric Heterostructures A nanoscale ferroelectric–dielectric heterostructure is illustrated atop a 3D NAND array, highlighting leakage-governed voltage division that amplifies the effective coercive voltage across the ferroelectric layer. In their Research Article (10.1002/aelm.202500702), Prasanna Venkatesan, Asif Khan, and co-workers, the dielectric insert is shown to redistribute the applied bias, enabling large memory windows without altering intrinsic switching kinetics. By providing a unified framework supported by experiments, circuit modeling, and defect-based simulations, the authors reveal a scalable pathway toward multi-level operation and high-density ferroelectric NAND technologies.